1 16xclk 2 txd 3 rcv 4 a0 16 v cc 15 oscin 14 oscout 13 powerdn 5 a1 6 a2 7 clk_sel 8 gnd 12 pulsemod 11 ir_txd 10 ir_rcv 9 nrst ir 3/16 encode/decode ic technical data HSDL-7001-2500 pc, tape and reel HSDL-7001#100-100pc, 50/tube features ? compliant with irda 1.0 physical layer specs ? interfaces with irda 1.0 compliant ir transceivers ? used in conjunction with standard 16550 uart ? transmits/receives either 1.63 m s or 3/16 pulse mode ? internal or external clock modes ? programmable baud rate ? 2.7-5.5 v operation ? 16 pin soic package applications ? interfaces with ir transceivers in: - computer applications: notebook computers sub-notebooks desktop pcs pdas printers dongle or other rs-232 adapter - telecom applications: modems fax machines pagers phones - handheld data collection: industrial medical transportation description the HSDL-7001 modulates and demodulates electrical pulses from hsdl-1001 infrared transceiver module and other irda-compliant transceivers. the HSDL-7001 can be used with a microcontroller/microprocessor that has a serial communication interface (uart). prior to com- munication, the processor selects the transmission baud rate. serial data is then transmitted or received at the prescribed data rate. the HSDL-7001 consists of two state machines C the sir (serial infrared) encode and sir decode blocks. it also contains a sequential block clock divide which synthesizes the required internal signal. the HSDL-7001 can be placed into the internal clock mode or external clock mode. an external crystal is needed for the internal clock mode. in applications where the external 16xclk signal is provided, a crystal is not needed. there are two data transmission modes. data can be transmitted and received in either a standard 3/16 modulation mode or a 1.63 m s pulse mode. schematic pin out sir
encode sir
decode txd ir_txd rcd ir_rcv a0 a1 a2 16xclk pulsemod clk_sel int_clock clock
divide /nrst
2 i/o pinout list pin name type function 1 16xclk digin positive edge triggered input clock that is set to 16 times the data (sixtnck) transmission baud rate. the encode and decode schemes require this signal. the signal is usually tied to a uarts baudout signal. the 16xclk may be provided by application circuitry if baudout is not available. this signal is required when the internal clock is not used. 2 /txd digin negative edge triggered input signal that is normally tied to the sout signal of the uart (serial data to be transmitted). data is modulated and output as ir_txd. 3 rcv digout output signal normally tied to sin signal of a uart (received serial data). rcv is the demodulated output of ir_rvc. 4 a0 digin clock multiplex signal 5 a1 digin clock multiplex signal 6 a2 digin clock multiplex signal 7 clk_sel digin used to activate either the internal or external clock. a high on this line activates the external clock (16xclk) and a low activates the internal clock. when the external clock is activated, the internal oscillator is put in powerdown mode. 8 gnd chip ground 9 /nrst digin active low signal used to reset the irda-sir encode & decode state machine. this signal can be tied to por (power on reset) or v cc . 10 /ir_rcv digin input from sir optoelectronics. input signal is a 3/16th or 1.6 m s pulse which is demodulated to generate rcv output signal. 11 ir_txd digout this is the modulated txd signal. 12 pulsemod digin a high level on this input puts the chip into the monoshot transmit (with mode. in this mode, when there is a negative transition on the txd pulldown) input, a rising edge on the internal transmit modulation state machine will activate a high pulse on ir_txd for 6 crystal clock cycles. with a 3.6864 mhz crystal, this corresponds to 1.63 m s. this mode cannot be used in conjunction with the 16xclk clock. it is meant to be used with the external crystal clock. by default, this input pin is pulled to gnd. 13 powerdn digin a high on this input puts only the internal oscillator cell (oscii) in (with powerdown mode. the cell is normally not powered down. pulldown) 14 oscout anaout oscillator output 15 oscin anain oscillator input 16 v cc power note: there are two methods of putting the internal oscillator cell in powerdown mode. whenever the clksel pin is asserted high (external clock selected) the oscillator cell is automatically put in powerdown mode, or whenever the powerdn pin is asserted high.
3 table 1. selection of internal clock rate from crystal oscillator selected clock rate (bps) a2 a1 a0 crystal freq. division 115200 0 0 0 divided by 2 57600 0 0 1 divided by 4 19200 0 1 0 divided by 12 9600 0 1 1 divided by 24 38400 1 0 0 divided by 6 4800 1 0 1 divided by 48 2400 1 1 0 divided by 96 test purpose 1 1 1 no division package dimensions ? notes:
1. dimensions a and b are datums
and t is a datum surface.
2. dimensioning and tolerancing per
ansi y14.5m, 1982.
3. controlling dimension: millimeter.
4. dimension a and b do not include
mold protrusion.
5. maximum mold protrusion 0.15 (0.006)
per side. p ? g d 0.25 (0.010) f mtbsas ? 16 pl. k seating
plane c 18 16 9 0.25 (0.010) f mbm r x 45 f j m millimeters inches min.
9.80
3.80
1.35
0.35
0.40
1.27 bsc
0.19
0.10
0? 5.80
0.25 max.
10.00
4.00
1.75
0.49
1.25
0.25
0.25
7? 6.20
0.50 dim.
a
b
c
d
f
g
j
k
m
p
r
min.
0.386
0.150
0.054
0.014
0.016
0.050 bsc
0.008
0.004
0? 0.229
0.010 max.
0.393
0.157
0.068
0.019
0.049
0.009
0.009
7? 0.244
0.019 r 8 pl. 16 1
4 encoding scheme the encoding scheme relies on a clock being present, which is set to 16 times the data transmission baud rate (16xclx). the encoder sends a pulse for every space or 0 that is sent on the txd line. on a high to low transition of the txd line, the generation of the pulse is delayed for 7 clock cycles of the 16xclk before the pulse is set high for 3 clock cycles (or 3/16th of a bit time) and then subsequently pulled low. this generates a 3/16th bit time pulse centered around the bit of information (0) that is being transmitted. decoding scheme arrival of a pulse. this pulse needs to be stretched to accommodate 1 bit time (or 16 16xclk cycles). every pulse that is received is translated into a 0 or space on the rxd line equal to 1 bit time. the irda-sir (serial infrared) decoding modulation method can be thought of as a pulse stretch- ing scheme. every high to low transition of the ir_rxd line signifies the for consecutive spaces, pulses with a 1 bit time delay are gener- ated in series. if a logic 1 (mark) is sent then the encoder does not generate a pulse. note 1: the stretched pulse must be at least 3/4 of a bit time in duration to be correctly inter- preted by a uart. note 2: it is recommended that txd remains high when not transmitting. this ensures the led is off and will not interfere with signal reception. 16xclk 16 cycles txd irtxd 7 cs 3 cs 16 cycles 16 cycles 16 cycles 16xclk 16 cycles irrxd rxd 3 cs 16 cycles 16 cycles 16 cycles
5 crystal
clk 6 crystal cycles int clk
(divby2) txd internal
irtxd
output irtxd
(monoshot) 1234567891011121314151617181920212223242526 the figure above illustrates the operation of the monoshot when the internal clock is set to divide by 2 mode, i.e., when a2=0, a1=0, and a0=0. a rising edge on the internal modulation state machine (irtxd output), will cause the output on the irtxd to go up for 6 crystal clock cycles. monoshot operation with a 3.6864 mhz clock, this corresponds to a pulse of 1.63 m s. the duration of this pulse is independent of the code a2, a1,a0 and is always 6 clock cycles of the crystal, corre- sponding to the monoshot operation.
6 absolute maximum ratings parameter symbol min. max. units storage temperature t s -65 +150 c operating temperature t a -40 +85 c output current i o -100 100 ma power dissipation [1] p max 0.46 w input/output voltage [2] v i /v o -0.5 v cc + 0.5 v power supply voltage v cc -0.5 7.0 v electrostatic protection v esd 4000 v notes: 1. maximum power dissipation is given for rth = 140 c/w (so 16 plastic). 2. all pins are protected from damage to static discharge by internal diode clamps to v cc and gnd. switching specifications (v cc = 2.7 to 5.5 v, t a = -20 to +85 c) parameter symbol min. typ. max. units conditions propagation delay time [1] t pd 80 ns output rise time [2] t rise 3.7 7.25 11.6 ns v cc = 5.5 v, cl = 50 pf 10 16 24 v cc = 2.7 v, cl = 50 pf output fall time [3] t fall 4.4 8.35 11.2 ns v cc = 5.5 v, cl = 50 pf 11 16 26 v cc = 2.7 v, cl = 50 pf output capacitance on output c out 50 pf pads used for simulation notes: 1. propagation delay time in the output buffer is the time taken from the input passing v cc /2 to the time of the output reaching v cc /2 with 50 pf as the output load. 2. the output rise time is the time taken for the outputs (rcv, ir_txd) to rise from 10% of the original value to 90% of the final value. 3. the output fall time is the time taken for the outputs (rcv, ir_txd) to fall from 90% of the original value to 10% of the final value.
7 recommended operating conditions (v cc = 2.7 to 5.5 v, t a = -20 to +85 c) parameter symbol min. typ. max. units conditions supply voltage v cc 2.7 5 5.5 v input voltage v i 0.0 v cc v ambient temperature t a -20 +85 c high level input voltage v ih 0.7 v cc v cc v low level input voltage v il 0 0.3 v cc v output high voltage v oh 2.2 v v cc = 2.7 v ioh = 2 ma output low voltage v ol 0.5 v v cc = 2.7 v iol = 2 ma output high voltage v oh 4.5 v v cc = 5.5 v ioh = 2 ma output low voltage v ol 0.5 v v cc = 5.5 v iol = 2 ma static power dissipation p stat 0.44 0.61 mw v cc = 5.5 v 0.11 0.15 mw v cc = 2.7 v dynamic power dissipation p dyn 11 16.5 mw v cc = 5.5 v 5.4 8.1 mw v cc = 2.7 v static current consumption i stat 80 110 m av cc = 5.5 v 40 54 m av cc = 2.7 v dynamic current consumption i dyn 23mav cc = 5.5 v 23mav cc = 2.7 v max clk frequency (16xclk) [1] f 16xclk 2 mhz minimum pulse width (ir_txd) [2] t mpw 1630 ns pulse width on monoshot t mpw 1630 1710 1730 ns (ir_txd and ir_rcv) value of pulldown resistor used on r dwn 114 152 256 k w powerdown & pulsemod input pins trigger low level input voltage vil_trig 0.7 0.8 0.9 v v cc = 2.7 v (for /nrst input pin) 1.9 1.95 2.00 v cc = 5.5 v trigger high level input voltage vih_trig 1.7 1.85 1.9 v v cc = 2.7 v (for /nrst input pin) 3.25 3.4 3.60 v cc = 5.5 v notes: 1. irda parameters. the max clk frequency represents the maximum clock frequency to drive the HSDL-7001s internal state machine. under normal circumstances, the clock input should not exceed 16* 115.2 kbps or 1.8432 mhz. this product can operate at higher clock rates, but the above is the recommended rate. 2. the minimum pulse width (t mpw ) represents the minimum pulse width of the encoded ir_txd pulse (and the ir_rcv pulse). as per the irda specifications, the minimum pulse width of the ir_txd and ir_rcv pulses should be 3*(1/1.8432 mhz) or 1.63 m s.
application circuits HSDL-7001 connection to uart HSDL-7001 connected to microcontroller txd HSDL-7001 application circuits-1 hsdl-1001 HSDL-7001 rcv ir_txd ir_rcv sout baudout txd 16xclk rcv uart 16550 sin v cc
10 k w 0.1 ? nrst txd HSDL-7001 application circuits-2 hsdl-1001 HSDL-7001 rcv ir_txd ir_rcv sdo i01 txd a0 rcv microcontroller sdi v cc
10 k w 0.1 ? i02 a1 i03 a2 i04 clk_sel i05 pulsemod i06 powerdn f = 3.6864 mhz 10 m w 15 pf 15 pf oscin oscout nrst note: powerdn can be used as a basic chip select.
the HSDL-7001 will not be able to receive or transmit data while powerdn is asserted. www.semiconductor.agilent.com data subject to change. copyright ? 2000 agilent technologies inc. obsoletes 5968-7456e 5980-0461e (4/00)
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